Transmission line pulse (TLP) testing of electrostatic discharge (ESD) devices is performed by using a high-voltage power supply to charge a cable at a voltage level, followed by discharging the cable into the ESD device, and then measuring the current through the ESD device. The test may be repeated at successively increasing voltage levels, enabling a current vs. voltage curve to be generated until the device fails. In that manner, the TLP testing determines a current level at which the ESD device fails.
Very-fast transmission line pulse testing (VFTLP) is a wafer-level test used to emulate charged device model (CDM) ESD stress. VFTLP includes high-current pulses (e.g., up to and greater than 10 A) with 250 ps rise time and 1 ns pulse width. ESD protection devices are characterized with VFTLP to predict their failure current and protection level during CDM stress. VFTLP failure currents may be reported in the ESD reference guide for each technology and included as a parameter in ESD compact models. Reflections of the pulse within the test system can cause premature failure of the device under test (DUT), which obscures the true forward failure point of the DUT.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.